ROM具有12位相位分辨率和内部DAC具有11位幅度分辨率。

The analog outputs of DAC can be selected between Normal-Hold mode (for the 1st

DAC的模拟输出可以选择正常保持模式之间（第一

Nyquist band ) and Return-to-Zero mode (for the 1st

奈奎斯特频段）和归零方式（第一

, 2nd

，第二

and 3rd

和第三

Nyquist band) operation.

奈奎斯特带）操作。

Sine waves can be generated up to 1st

正弦波可以产生高达第一

Nyquist band near 1.4 GHz (at a 2.8-GHz clock rate) with

奈奎斯特频段在1.4 GHz（在2.8 GHz时钟速率）与

Normal-Hold mode of DAC or up to 3rd

DAC或第三正常保持模式

Nyquist band around 4 GHz with Return-to-Zero mode

奈奎斯特频段在4 GHz归零模式

of DAC. The initial phase can be reset to any degree, determined by phase bit inputs, to start with.

DAC。初始阶���可以被重置到任何程度，由相位位输入确定，开始。

The chip has a pair of complementary analog outputs with 50-??6??8 back terminations. The

该芯片具有一对50??6??8回到终端互补的模拟输出。这个

frequency of output waveforms can be controlled by the thirty frequency control bits, Vi[0:29].

输出波形的频率可由三十个频率控制位控制，VI [ 0:29 ]。

The phase of output waveforms can be modulated by the 11-bit Pi[0:10] phase modulation

输出波形的相位可以由11位PI [ 0:10 ]相位调制

inputs. The DS875 accepts either differential clock inputs or a single-ended clock input and

输入。的ds875接受差分时钟输入或单端时钟输入

features 50-??6??8 on-chip back terminations to ground. Both the frequency word and phase word

特点50??6??8片回终端接地。频率字和相位词

inputs accept LVTTL/CMOS input levels. Differential synchronization input SyncI_P/N

输入接受LVTTL / CMOS输入级。差动同步输入synci_p / N

provides synchronization for multiple chip applications and start each chip with the same phase of

提供多个芯片应用程序的同步，并开始每个芯片具有相同的相位

synchronization outputs SyncO_P/N ready to accept frequency word and strobe inputs. The

同步输出synco_p /正准备接受频率字和选通输入。这个

synchronous Strobe inputs are latched by internal generated divide-by-8 clocks which were also

同步选通输入锁存由内部产生的时钟进行分频8

sent to the output pins SyncO_P/N. SyncO_P/N. can be used as a reference to synchronize the

发送到输出引脚synco_p，synco_p，可以作为参考来同步

frequency word, phase word and strobe signal input timing alignment to the internal divide-by-8

频率字，相字和选通信号输入时序调整到内部分频8

clock to latch all input data properly. The Reset is asynchronous to minimize clock latencies of

时钟锁定所有输入数据正确。复位是异步的，以尽量减少时钟延迟

effectiveness on the analog outputs. The internal timing was optimized to avoid clock slipping

模拟输出的有效性。内部定时进行了优化，以避免时钟打滑

during frequency word and/or phase word transition or after reset. The analog outputs of DAC

在频率字和/或相位字过渡或复位后。DAC的模拟输出

can be selected between Normal Hold mode (for the 1st

可以选择正常举行模式（为第一

Nyquist band ) or Return-to-Zero mode

奈奎斯特频段）或归零模式

(for the 1st

（第一

, 2nd

，第二

and 3rd

和第三

Nyquist band) operation. Combining with selectable filters, effectively

奈奎斯特带）操作。结合可选的过滤器，有效

ultra-broadband signals from DC to the 3rd

超宽带信号从直流到第三

Nyquist band can be generated. Only a single –5V

奈奎斯特频段可以生成。只有一个–5V

power supply is required.

需要电源。